Dell PowerEdge 6650

Chipset

The PowerEdge 6650 incorporates the ServerWorks Corporation GCHE (Grand Champion High End) chipset for system memory, I/O and processor interfacing. The GCHE is designed to support Intel's next generation 32-bit processor family, new DDR Memory technology and the advanced PCI-X system I/O bus.

Detailed Specifications

The ServerWorks GCHE chipset supports a 400MHz front side bus and has multiple peer-to-peer PCI-X buses. The benefit of having peer-to-peer PCI-X buses combined with 64-bit/100MHz technology is that high load, high speed traffic can be allocated to several high speed PCI-X buses and separated from slower traffic, thus increasing overall system performance.

The theoretical I/O bandwidth of the PowerEdge 66X0 is 5GB/s compared to 933MB/s on the PowerEdge 64X0 (~4X improvement).

The ServerWorks GCHE chipset supports the redundant memory features known as "ChipKill", "Spare Bank Memory " and "Memory Mirroring". These features provide protection from memory errors and will be covered in the memory technology section.

The GCHE ServerSet consists of four primary devices and can be configured into a 2-way (GCHE LITE) or 4-way (GCHE CLASSIC) configuration.

1. CMIC - champion memory and I/O controller
2. CSB5 - champion south bridge
3. CIOB30 - champion I/O bridge
4. REMC - reliability enhanced memory controller

CMIC Champion Memory & I/O Controller (North Bridge)

The CMIC provides a high-speed interface between the main system memory, processor and system I/O bus. The function blocks of the CMIC controller consist of the Host, IMBus and DDR SDRAM interface.

• 3.2GB/s host bus interface with IOQ depth of 12
• 36-bit 200MHz address bus
• 64-bit 400MHz data bus
• 16-deep memory burst, 8-deep memory read queue, 4-deep memory single write queue
• Parity and data inversion support

• Interconnect path for Connects CMIC, CIOB and CSB5
• 1.6GB/s bandwidth (2B @ 400MHz each direction) interface to PCI-X subsystem
• Narrow 38-pin interface
• 16 read and 16 write concurrent request supported by independent tags
• Out of order, barrier and coherency management support via required command set

• 100MHz double data rate memory interface = 200MHz
• 288-bit-wide memory array
• Registered DDRAM support
• 16Mx72, 32Mx72, 64Mx72, 128Mx72 or 256x72 DIMM support
• Memory scrubbing, single-bit correction and multi-bit error detection

Champion South Bridge (CSB5)

The CSB5 operates as the PCI to LPC address / data bridge for the PowerEdge 6650 system. The CSB5 supports the Advanced Configuration and Power Management Interface Specification (ACPI) Ver. 1.0.

• PCI-LPC Address / Data Bridge
• PCI Master
• 7 channel 8237-compatible DMA controller
• 8253 counter / timer
• I2C support
• DMA 66 support - IDE
• Enhanced ACPI support
• SMBus
• ¼ IMBus support (Narrow 14 pin interface)
• Dual USB port support

I/O Bridge (CIOB30)

The CIOB30 is an integrated I/O bridge for the IMB and PCI-X I/O subsystem. The interface provides a high performance path between the IMB and multiple I/O buses.

• 400MHz IMB support
• Concurrency between IMB and PCI-X buses
• 8 deep outbound request queue (IMB to PCI-X)
• 8 deep IMP to PCI (X) memory write posting
• Caching with 16-deep, 32-byte I/O cache for PCI
• Parity protection
• VGA compatible addressing support
• Multiple I/O APIC support
• Peer-to-peer transfer support

Reliability Enhanced Memory Controller (REMC)

The REMC is designed to support Data and Address path mode operation. A four way interleaved memory system requires five REMCs. Four of the REMCs are used in the data path and the 5th RMC is used in address path mode and generates multiple copies of address and control data for the memory system.

• 288-bit data path
• ECC support
• Supports concurrent read and write accesses
• Supports x4 and x8 based registered DDR DIMMs.

PCI Expansion Slots

The PowerEdge 6650 supports 7 64-bit/100MHz slots on peer PCI-X buses 2, 3, 4, 5, and 6. There are two slots per bus for each of these PCI bus segments. These slots accept PCI cards designed for 66MHz or 33MHz and will operate in PCI mode at the lowest common frequency for that bus.

PCI-X cards may co-exist with PCI cards on a bus and will operate in PCI mode. The slots also will operate in PCI-X mode if populated exclusively by PCI-X cards. 133 MHz PCI-X adapters will operate at 100 MHz in these slots. 66 MHz PCI-X adapters present will bring the clock speed down to 66Mhz.

All PCI-X slots are 3V-signaling environment compatible and will accept either 3V PCI and PCI-X cards or Universal PCI cards. The 32-bit/33Mhz PCI slot is a 5V-signaling environment and will accept either 5V PCI or Universal PCI cards

Embedded Server Management (ESM III)

The PowerEdge 6650 system implements circuitry for Embedded Server Management (ESM III). ESM III is the new generation of Dell Embedded Server Management and is compliant with the Intelligent Platform Management Interface (IPMI), v1.0.

The BMC (Baseboard Micro Controller) is the predominant resource in the ESM III implementation. A QLogic Zircon microcontroller, acting as the BMC, is the interface between the host system (i.e., server management software) and the peripheral devices.

These peripheral devices include the Power Distribution Board (PDB), the power supplies (PS), the backplane and corresponding SCSI Daughter Card (SDC), control-panel with semi-intelligent display, the DRAC III, and any external devices connected via a ICMB link. Each of these peripheral devices, including the BMC, has various environmental sensors and controls that are made available to the server management software via the IPMI interface protocol.

Peripheral devices that do not support the IPMI specification may still communicate with the ESM III. In this situation, the BMC acts as liaison by hiding these peripheral devices yet providing the sensor data and controls to the host. This allows these sensors and controls to function as if they are integrated as part of the BMC.