Dell PowerEdge 4600

Chipset

The PowerEdge 4600 system board incorporates the ServerWorks GCHE (Grand Champion High End) chipset for system memory, I/O and processor interfacing. The GCHE is designed to support Intel's next generation 32-bit processor family, new DDR Memory technology and the advanced PCI-X system I/O bus.

The GCHE ServerSet comprises of four primary devices:

• CMIC - champion memory and I/O controller
• CIOB30 - champion I/O bridge
• REMC - reliability enhanced memory controller
• CSB5 - champion south bridge

The GCHE can be configured into a 2 -way (GCHE LITE) or 4-way (GCHE CLASSIC) configuration.

CMIC Champion Memory & I/O Controller (North Bridge)

The CMIC provides a high-speed interface between the main system memory, processor and system I/O bus. The function blocks of the CMIC controller consist of the Host, IMBus and DDR SDRAM interface.

• 3.2GB/s Host Bus interface with IOQ depth of 12
• 36-bit 200MHz address bus
• 64-bit 400MHz data bus
• 16-deep Memory Burst, 8-deep Memory Read queue, 4-deep Memory single write queue
• Parity and Data Inversion support

• Interconnect path for Connects CMIC, CIOB and CSB5
• 1.6GB/s Bandwidth (2B @ 400MHz each direction) interface to PCI-X subsystem
• Narrow 38 Pin Interface
• 16 Read and 16 Write concurrent request supported by independent tags
• Out of order, barrier and coherency management support via required command set

• 100MHz Double data rate memory interface = 200MHz
• 288-bit-wide memory array
• Registered DDRAM Support
• 16Mx72, 32Mx72, 64Mx72, 128Mx72 or 256x72 DIMM support
• Memory scrubbing, single-bit correction and multi-bit error detection

Champion South Bridge (CSB5)

The CSB5 operates as the PCI to LPC address / data bridge for the PowerEdge 4600 system. The CSB5 supports the Advanced Configuration and Power Management Interface Specification (ACPI) version 1.0.

• PCI<->LPC Address / Data Bridge
• PCI Master
• 7 Channel 8237 Compatible DMA controller
• 8253 Counter / Timer
• I2C Support
• DMA 66 Support - IDE
• Enhanced ACPI Support
• SMBus
• ¼ IMBus support (Narrow 14 pin interface)
• Dual USB port support

I/O Bridge (CIOB30)

The CIOB30 is an integrated I/O bridge for the IMB and PCI(X) I/O subsystem. The interface provides a high performance path between the IMB and multiple I/O buses.

• 400MHz IMB support
• Concurrency between IMB and PCI (X) buses
• 8 deep outbound request queue (IMB to PCI (X)
• 8 deep IMP to PCI (X) memory write posting
• Caching with 16-deep, 32-byte I/O cache for PCI
• Parity protection
• VGA compatible addressing support
• Multiple I/O APIC support
• Peer to Peer transfer support

Reliability Enhanced Memory Controller (REMC)

The REMC is designed to support Data and Address path mode operation. A four-way interleaved memory system requires five REMCs. Four of the REMCs are used in the data path; the fifth REMC is used in address path mode and generates multiple copies of address and control for the memory system.

• 288-bit data path
• ECC Support
• Supports concurrent read and write accesses
• Supports x4 and x8 based Registered DDR DIMMs.

PCI Expansion Slots

The PowerEdge 4600 provides seven slots for PCI/PCI-X expansion cards. PCI-X is an extension of the widely accepted PCI standard for data transfer between CPUs and I/O peripherals and is becoming widely used by manufacturers in order to speed the flow of data within servers, storage area networks and network switches. Backwards compatible with the high performance PCI local bus specification, PCI-X offers an immediate solution to the increased I/O requirements for high-bandwidth applications such as Gigabit Ethernet, Fibre Channel, Ultra3 SCSI and high-performance graphics. PCI-X supports 32-bit and 64-bit operations at frequencies up to 100MHz, allowing data throughput up to 800MB/s.

Embedded Server Management (ESM III)

The PowerEdge 4600 system implements circuitry for Embedded Server Management (ESM III). ESM III is the new generation of Dell Embedded Server Management and is compliant with the Intelligent Platform Management Interface (IPMI), v1.0.

See http://developer.intel.com/design/servers/ipmi/index.htm for details on IPMI.

The BMC (Baseboard Micro Controller) is the primary resource in ESM III implementation. A QLogic Zircon micro controller, acting as the BMC, is the interface between the host system (i.e., server management software) and the periphery devices. These periphery devices include the Power Distribution Board (PDB), the power supplies (PS), the backplane and corresponding SCSI Daughter Card (SDC), control-panel with semi-intelligent display, the DRAC 3, and any external devices connected via a ICMB link. Each of these periphery devices, including the BMC, has various environmental sensors and controls that are made available to the server management software via the IPMI interface protocol.

For periphery devices that do not support the IPMI specification, the BMC acts as liaison hiding these periphery devices yet providing the sensor data and controls to the host as if said sensors and controls were integrated as part of the BMC.

Memory

• PC200/DDR (double data rate) technology (100 MHz clock)
• Support for up to 6 GB of memory per card for a total system memory of 12 GB
• Support for four way interleaving
• Support for x4 or x8 ChipKill
• I2C control of DIMM clocks (clocks to unused slots can be disabled)